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exar corporation, 48720 kato road, fremont, ca 94538 ? (510) 668-7000 ? fax (510) 668-7017 st16c550 rev. 5.01 plcc package uart with 16-byte fifo?s 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 rclk rx n.c. tx cs0 cs1 -cs2 -baudout reset -op1 -dtr -rts -op2 n.c. int -rxrd y a0 a1 a2 d4 d3 d2 d1 d0 n.c . vcc -ri -cd -dsr -ct s xtal1 xtal2 -iow iow gnd n.c. -ior ior -ddis - txrdy -as st16c550cj44 april 2005 general description the st16c550 (550) is a universal asynchronous re- ceiver and transmitter with 16 byte transmit and receive fifo. it operates at 2.97 to 5.5 volts. a programmable baud rate generator can select transmit and receive clock rates from 50 bps to 1.5 mbps. the st16c550 is an improved version of the ns16c550 uart with higher operating speed and lower access time. the st16c550 on board status registers provides the error conditions, type and status of the transfer operation being performed. included is complete mo- dem control capability, and a processor interrupt system that may be software tailored to the user?s requirements. the st16c550 provides internal loop- back capability for on board diagnostic testing. the st16c550 is available in 40 pin pdip, 44 pin plcc, and 48 pin tqfp packages. it is fabricated in an advanced cmos process to achieve low drain power and high speed requirements. features ? pin to pin and functionally compatible to the industry standard 16c550 ? 2.97 to 5.5 volt operation ? 24mhz clock operation at 5v ? 16mhz clock operation at 3.3v ? 16 byte transmit fifo ? 16 byte receive fifo with error flags ? full duplex operation ? transmit and receive control ? four selectable receive fifo interrupt trigger levels ordering information part number package operating temperature device status st16c550cp40 40-lead pdip 0 c to + 70 c active. see the st16c550cq48 for new designs. st16c550cj44 44-lead plcc 0 c to + 70 c active st16c550cq48 48-lead tqfp 0 c to + 70 c active st16c550ip40 40-lead pdip -40 c to + 85 c active. see the st16c550iq48 for new designs. st16c550ij44 44-lead plcc -40 c to + 85 c active st16c550iq48 48-lead tqfp -40 c to + 85 c active ? standard modem interface ? compatible with st16c450 ? low operating current ( 1.2ma typ.)
st16c550 2 rev. 5.01 48 pin tqfp package 40 pin dip package figure 1, package description, st16c550 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. d5 d6 d7 rclk n.c. rx tx cs0 cs1 -cs2 - baudout n.c. xtal1 xtal2 -iow iow gnd -ior ior n.c. -ddis -txrdy -as n.c. reset -op1 -dtr -rts -op2 int -rxrd y a0 a1 a2 n.c. n.c . d4 d3 d2 d1 d0 vcc -ri -cd -ds r -ct s n.c . st16c550cq48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 d0 d1 d2 d3 d4 d5 d6 d7 rclk rx tx cs0 cs1 -cs2 - baudout xtal1 xtal2 -iow iow gnd vcc -ri -cd -dsr -cts reset -op1 -dtr -rts -op2 int -rxrd y a0 a1 a2 -as -txrd y -ddis ior -ior st16c550cp40
st16c550 3 rev. 5.01 figure 2, block diagram d0-d7 -ior,ior - iow,iow reset a0-a2 -as cs0,cs1 -cs2 int -rxrdy -txrdy -dtr,-rts -op1,-op 2 -cts -ri -cd -dsr tx rx data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers transmit shift register receive fifo registers receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 rclk xtal2 - baudout -ddis
st16c550 4 rev. 5.01 symbol pin signal pin description 40 44 48 type symbol description a0 28 31 28 i address-0 select bit internal registers address selection. a1 27 30 27 i address-1 select bit internal registers address selection. a2 26 29 26 i address-2 select bit internal registers address selection. ior 22 25 20 i read data strobe. its function is the same as -ior (see - ior), except it is active high. either an active -ior or ior is required to transfer data from 16c550 to cpu during a read operation. connect to logic 0 when using -ior. cs0 12 14 9 i chip select-0. logical 1 on this pin provides the chip select- 0 function. connect cs0 to logic 1 if using cs1 or -cs2. cs1 13 15 10 i chip select-1. logical 1 on this pin provides the chip select- 1 function. connect cs1 to logic 1 if using cs0 or -cs2. -cs2 14 16 11 i chip select -2. logical 0 on this pin provides the chip select- 2 function. connect to logic 0 if using cs0 or cs1. iow 19 21 17 i write data strobe. its function is the same as -iow (see - iow), but it acts as an active high input signal. either -iow or iow is required to transfer data from the cpu to st16c550 during a write operation. connect to logic 0 when using -iow. -as 25 28 24 i address strobe. a logic 1 transition on -as latches the state of the chip selects and the register select bits, a0-a2. this input is used when address and chip selects are not stable for the duration of a read or write operation, i.e., a micropro- cessor that needs to de-multiplex the address and data bits. if not required, the -as input can be permanently tied to a logic 0. d0-d7 1-8 2-9 43-47 2-4 i/o data bus (bi-directional) - these pins are the eight bit, tri- state data bus for transferring information to or from the controlling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. gnd 20 22 18 pwr signal and power ground.
st16c550 5 rev. 5.01 symbol pin signal pin description 40 44 48 type symbol description -ior 21 24 19 i read data strobe (active low strobe). a logic 0 on this pin transfers the contents of the st16c550 data bus to the cpu. connect to logic 1 when using ior. -iow 18 20 16 i write data strobe (active low strobe). a logic 0 on this pin transfers the contents of the cpu data bus to the addressed internal register. connect to logic 1 when using iow. int 30 33 30 o interrupt request (active high). interrupts are enabled in the interrupt enable register (ier), and when an interrupt con- dition exists. interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. -rxrdy 29 32 29 o receive ready. when operating in the fifo mode, one of two types of dma signaling can be selected using the fifo control register bit-3. when operating in the st16c450 mode, only dma mode ?0? is allowed. mode ?0? supports single transfer dma in which a transfer is made between cpu bus cycles. mode ?1? supports multi-transfer dma in which multiple transfers are made continuously until the receiver fifo has been emptied. in dma mode ?0? -rxrdy is low, when there is at least one character in the receiver fifo or receive holding register. in dma mode ?1?, -rxrdy is low, when the trigger level or the time-out has been reached. -txrdy 24 27 23 o transmit ready. when operating in the fifo mode, one of two types of dma signaling can be selected using the fifo control register bit-3. when operating in the st16c450 mode, only dma mode ?0? is allowed. mode ?0? supports single transfer dma in which a transfer is made between cpu bus cycles. mode ?1? supports multi-transfer dma in which multiple transfers are made continuously until the transmit fifo has been filled. -baudout 15 17 12 o baud rate generator output. this pin provides the 16x clock of the selected data rate from the baud rate generator. the rclk pin must be connected externally to -baudout when the receiver is operating at the same data rate.
st16c550 6 rev. 5.01 symbol pin signal pin description 40 44 48 type symbol description -ddis 23 26 22 o drive disable. this pin goes to a logic 0 when the external cpu is reading data from the st16c550. this signal can be used to disable external transceivers or other logic func- tions. -op1 34 38 34 o output-1 (user defined) - see bit-2 of modem control register (mcr bit-2). reset 35 39 35 i reset. (active high) - a logic 1 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see st16c550 external reset conditions for initial- ization details.) rclk 9 10 5 i receive clock input. this pin is used as external 16x clock input to the receiver section. external connection to - baudout pin is required in order to utilize the internal baud rate generator. -op2 31 35 31 o output-2 (user defined). this pin provides the user a general purpose output. see bit-3 modem control register (mcr bit-3). vcc 40 44 42 pwr power supply input. xtal1 16 18 14 i crystal or external clock input - functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit. an external 1 m ? resistor is required between the xtal1 and xtal2 pins (see figure 3). alternatively, an external clock can be connected to this pin to provide custom data rates (programming baud rate generator section). xtal2 17 19 15 o output of the crystal oscillator or buffered clock - (see also xtal1). crystal oscillator output or buffered clock output. -cd 38 42 40 i carrier detect (active low) - a logic 0 on this pin indicates that a carrier has been detected by the modem.
st16c550 7 rev. 5.01 symbol pin signal pin description 40 44 48 type symbol description -cts 36 40 38 i clear to send (active low) - a logic 0 on the -cts pin indicates the modem or data set is ready to accept transmit data from the st16c550. status can be tested by reading msr bit-4. this pin has no effect on the uart?s transmit or receive operation. -dsr 37 41 39 i data set ready (active low) - a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uart?s transmit or receive operation. -dtr 33 37 33 o data terminal ready (active low) - a logic 0 on this pin indicates that the st16c550 is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr bit-0 will set the -dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr bit-0, or after a reset. this pin has no effect on the uart?s transmit or receive operation. -ri 39 43 41 i ring indicator (active low) - a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. -rts 32 36 32 o request to send (active low) - a logic 0 on the -rts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register (mcr bit-1) will set this pin to a logic 0 indicating data is available. after a reset this pin will be set to a logic 1. this pin has no effect on the uart?s transmit or receive operation. rx 10 11 7 i receive data - this pin provides the serial receive data input to the st16c550. a logic 1 indicates no data or an idle channel. during the local loop-back mode, the rx input pin is disabled and tx data is internally connected to the uart rx input, internally, see figure 12. tx 11 13 8 o transmit data - this pin provides the serial transmit data from the st16c550, the tx signal will be a logic 1 during reset, idle (no data). during the local loop-back mode, the tx pin is set to a logic 1 and tx data is internally connected to the uart rx input, see figure 12.
st16c550 8 rev. 5.01 general description the st16c550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to- parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). data integ- rity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. the st16c550 represents such an integration with greatly enhanced features. the st16c550 is fabricated with an advanced cmos process. the st16c550 is an upward solution that provides 16 bytes of transmit and receive fifo memory, instead of 1 byte provided in the 16c450. the st16c550 is designed to work with high speed modems and shared network environments, that require fast data process- ing time. increased performance is realized in the st16c550 by the larger transmit and receive fifo?s. this allows the external processor to handle more networking tasks within a given time. the 4 selectable levels of fifo trigger provided for maximum data throughput performance especially when operating in a multi-channel environment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the st16c550 is capable of operation to 1.5mbps with a 24 mhz crystal or external clock input. with a crystal of 14.7464 mhz and through a software option, the user can select data rates up to 460.8kbps or 921.6kbps. functional descriptions internal registers the st16c550 provides 12 internal registers for monitoring and control. these registers are shown in table 3 below. these registers function as data hold- ing registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control register (fcr), line status and control registers, (lcr/lsr), modem status and control registers (mcr/msr), program- mable data rate (clock) control registers (dll/dlm), and a user assessable scratchpad register (spr).
st16c550 9 rev. 5.01 table 2, internal register decode a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, lcr/lsr, spr): 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register reserved 1 1 0 modem status register reserved 1 1 1 scratchpad register scratchpad register baud rate generator registers (dll/dlm). accessible only when lcr bit-7 is set to 1. 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch fifo operation the 16 byte transmit and receive data fifo?s are enabled by the fifo control register (fcr) bit-0. with 16c550 devices, the user can set the receive trigger level but not the transmit trigger level. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the load- ing of a character or the receive trigger level has not been reached. time-out interrupts when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier bit-0). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case the st16c550 fifo may hold more characters than the programmed trigger level. fol- lowing the removal of a data byte, the user should recheck lsr bit-0 for additional characters. a re- ceive time out will not occur if the receive fifo is empty. the time out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read (see figure 10, re- ceive time-out interrupt). the actual time out value is t ( t ime out length in bits) = 4 x p ( p rogrammed word length) + 12. to convert the time out value to a character value, the user has to consider the com- plete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1x, 1.5x, or 2x bit times. example -a: if the user programs a word length of 7, with no parity and one stop bit, the time out will be: t = 4 x 7( programmed word length) +12 = 40 bit times. the character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out ex-
st16c550 10 rev. 5.01 ample: t = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. example -b: if the user programs the word length = 7, with parity and one stop bit, the time out will be: t = 4 x 7(programmed word length) + 12 = 40 bit times. character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. programmable baud rate generator the st16c550 supports high speed modem tech- nologies that have increased input data rates by employing data compression schemes. for example a 33.6kbps modem that employs data compression may require a 115.2kbps input data rate. a 128.0kbps isdn modem that supports data compression may need an input data rate of 460.8kbps. the st16c550 can support a standard data rate of 921.6kbps. the programmable baud rate generator is capable of accepting an input clock up to 24 mhz, as required for supporting a 1.5mbps data rate. the st16c550 can be configured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/ 22 pf load) is connected externally between the xtal1 and xtal2 pins, with an external 1 m ? resistor across it. alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. see figure 3 for crystal oscillator connection. the generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the st16c550 divides the basic crystal or external clock by 16. the frequency of the -baudout output pin is exactly 16x (16 times) of the selected baud rate (-baudout =16 x baud rate). customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sec- tions of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired final baud rate. the example in table 3 below shows selectable baud rates when using a 1.8432 mhz crystal. for custom baud rates, the divisor value can be calcu- lated using the following equation: divisor (in decimal) = (xtal1 clock frequency) / (serial data rate x 16) table 3, baud rate generator programming table (1.8432 mhz clock): output user user dlm dll baud rate 16 x clock 16 x clock program program divisor divisor value value (decimal) (hex) (hex) (hex) 50 2304 900 09 00 75 1536 600 06 00 150 768 300 03 00 300 384 180 01 80 600 192 c0 00 c0 1200 96 60 00 60 2400 48 30 00 30 4800 24 18 00 18 7200 16 10 00 10 9600 12 0c 00 0c 19.2k 6 06 00 06 38.4k 3 03 00 03 57.6k 2 02 00 02 115.2k 1 01 00 01
st16c550 11 rev. 5.01 dma operation the st16c550 fifo trigger level provides additional flexibility to the user for block mode operation. the user can optionally operate the transmit and receive fifo?s in the dma mode (fcr bit-3). the dma mode affects the state of the -rxrdy and -txrdy output pins. the following tables show this: -rxrdy pin: non-dma mode dma mode 1 = fifo empty 0 to 1 transition when fifo empties 0 = at least 1 byte 1 to 0 transition when fifo in fifo reaches trigger level, or timeout occurs -txrdy pin: non-dma mode dma mode 1 = at least 1 byte 1 = fifo is full in fifo 0 = fifo empty 0 = fifo has at least 1 empty location loop-back mode the internal loop-back capability allows onboard diag- nostics. in the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. in this mode msr bits 4-7 are also disconnected. however, mcr register bits 0-3 can be used for controlling loop-back diagnostic test- ing. in the loop-back mode -op1 and -op2 in the mcr register (bits 0-1) control the modem -ri and -cd inputs respectively. mcr signals -dtr and -rts (bits 0-1) are used to control the modem -cts and -dsr inputs respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their associ- ated interface pins, and instead are connected together internally (see figure 4). the -cts, -dsr, -cd, and -ri are disconnected from their normal modem control inputs pins, and instead are connected internally to - dtr, -rts, -op1 and -op2. loop-back test data is entered into the transmit holding register via the user data bus interface, d0-d7. the transmit uart serial- izes the data and passes the serial data to the receive uart via the internal loop-back connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface, d0-d7. the user optionally compares the received data to the initial transmitted data for verifying error free operation of the uart tx/rx circuits. in this mode , the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational. the interrupts are still controlled by the ier. figure 3, typical external crystal oscil- lator connection c1 22-47pf c2 22-47pf y1 1.8432 - 24 mhz r1 0-120 (optional) r2 1m xtal1 xtal2
st16c550 12 rev. 5.01 figure 4, internal loop-back mode diagram d0-d7 -ior,ior - iow,iow reset a0-a2 -as cs0,cs1 -cs2 int -txrdy -rxrdy tx rx data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers transmit shift register receive fifo registers receive shift register inter connect bus lines & control signals clock & baud rate generator xtal1 rclk xtal2 -baudout -cd -rts -dtr -ri -dsr -cts -op1 -op2 mcr bit-4=1 -ddis vcc vcc vcc vcc vcc
st16c550 13 rev. 5.01 register functional descriptions the following table delineates the assigned bit functions for the twelve st16c550 internal registers. the assigned bit functions are more fully defined in the following paragraphs. table 4, st16c550 internal registers a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *2 general register set 0 0 0 rhr [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier [00] 0000 modem receive transmit receive status line holding holding interrupt status register register interrupt 0 1 0 fcr [00] rcvr rcvr 0 0 dma xmit rcvr fifo trigger trigger mode fifo fifo enable (msb) (lsb) select reset reset 0 1 0 isr [01] fifo?s fifo?s 0 0 int int int int enabled enabled priority priority priority status bit-2 bit-1 bit-0 0 1 1 lcr [00] divisor set set even parity stop word word latch b reak parity parity enable bits length length enable bit-1 bit-0 1 0 0 mcr [00] 0 0 0 loopback -op2 -op1 -rts -dtr enable 1 0 1 lsr [60] fifo trans. trans. break framing parity overrun receive data empty holding interrupt error error error data error empty ready 1 1 0 msr [x0] cd ri dsr cts delta delta delta delta -cd -ri -dsr -cts 1 1 1 spr [ff] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor registers. accessible when lcr bit-7 is set to logic 1. note 1* 0 0 0 dll [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm [xx] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 note *1: the brg registers are accessible only when lcr bit-7 is set to a logic 1. note *2: the value represents the register?s initialized hex value. an ?x? signifies a 4-bit un-initialized nibble.
st16c550 14 rev. 5.01 transmit and receive holding register the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr is empty. the thr empty flag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = at least one byte in fifo / thr, logic 1= fifo/thr empty). the serial receive section also contains an 8-bit receive holding register, rhr. receive data is removed from the st16c550 and receive fifo by reading the rhr register. the receive section pro- vides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. after 7 1/2 clocks the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. receiver status codes will be posted in the lsr. interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the st16c550 int output pin. ier vs receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: a) the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b) fifo status will also be reflected in the user accessible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. c) the data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. ier vs receive/transmit fifo polled mode op- eration when fcr bit-0 equals a logic 1; resetting ier bits 0-3 enables the st16c550 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a) lsr bit-0 will be a logic 1 as long as there is one byte in the receive fifo. b) lsr bit 1-4 will indicate if an overrun error occurred. c) lsr bit-5 will indicate when the transmit fifo is empty. d) lsr bit-6 will indicate when both the transmit fifo and transmit shift register are empty. e) lsr bit-7 will indicate any fifo data errors. ier bit-0: logic 0 = disable the receiver ready interrupt. (normal default condition) logic 1 = enable the receiver ready interrupt. ier bit-1: logic 0 = disable the transmitter empty interrupt. (normal default condition) logic 1 = enable the transmitter empty interrupt. ier bit-2: logic 0 = disable the receiver line status interrupt. (normal default condition) logic 1 = enable the receiver line status interrupt.
st16c550 15 rev. 5.01 ier bit-3: logic 0 = disable the modem status register interrupt. (normal default condition) logic 1 = enable the modem status register interrupt. ier bit 4-7: not used and set to ?0?. fifo control register (fcr) this register is used to enable the fifo?s, clear the fifo?s, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: dma mode: see description and dma tables on page 11. fcr bit-0: logic 0 = disable the transmit and receive fifo. (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a ?1? when other fcr bits are written to or they will not be programmed. fcr bit-1: logic 0 = no fifo receive reset. (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-2: logic 0 = no fifo transmit reset. (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift regis- ter is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-3: logic 0 = set dma mode ?0?. (normal default condi- tion) logic 1 = set dma mode ?1.? transmit operation in mode ?0?: when the st16c550 is in the st16c450 mode (fifo?s disabled, fcr bit-0 = logic 0) or in the fifo mode (fifo?s enabled, fcr bit-0 = logic 1, fcr bit- 3 = logic 0) and when there are no characters in the transmit fifo or transmit holding register, the - txrdy pin will be a logic 0. once active the -txrdy pin will go to a logic 1 after the first character is loaded into the transmit holding register. receive operation in mode ?0?: when the st16c550 is in mode ?0? (fcr bit-0 = logic 0) or in the fifo mode (fcr bit-0 = logic 1, fcr bit- 3 = logic 0) and there is at least one character in the receive fifo, the -rxrdy pin will be a logic 0. once active the -rxrdy pin will go to a logic 1 when there are no more characters in the receiver. transmit operation in mode ?1?: when the st16c550 is in fifo mode ( fcr bit-0 = logic 1, fcr bit-3 = logic 1 ), the -txrdy pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode ?1?: when the st16c550 is in fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 1) and the trigger level has been reached, or a receive time out has occurred, the -rxrdy pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. fcr bit 4-5: not used. fcr bit 6-7: these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. how- ever the fifo will continue to be loaded until it is full. bit-7 bit-6 rx fifo trigger level 00 1 01 4 10 8 11 14
st16c550 16 rev. 5.01 interrupt status register (isr) the st16c550 provides four levels of prioritized inter- rupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowl- edged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after rereading the interrupt status bits. the interrupt source table 5 (below) shows the data values (bit 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: table 5, interrupt source table priority [isr] level bit-3 bit-2 bit-1 bit-0 source of the interrupt x 0001no interrupt pending 1 0110 lsr (receiver line status register) 2 0100 rxrdy (received data ready) 2 1100 rxrdy (receive data time out) 3 0010 txrdy ( transmitter holding register empty) 4 0000 msr (modem status register)
st16c550 17 rev. 5.01 isr bit-0: logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending. (normal default condi- tion) isr bit 1-3: (logic 0 or cleared is the default condition) these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see interrupt source table). isr bit 4-5 : not used and set to ?0?. isr bit 6-7: (logic 0 or cleared is the default condition) these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifo?s are enabled line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr bit 0-1: (logic 0 or cleared is the default condi- tion) these two bits specify the word length to be transmit- ted or received. bit-1 bit-0 word length 00 5 01 6 10 7 11 8 lcr bit-2: (logic 0 or cleared is the default condition) the length of stop bit is specified by this bit in conjunction with the programmed word length. bit-2 word length stop bit length (bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 lcr bit-3: parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmis- sion, receiver checks the data and parity for transmis- sion errors. lcr bit-4: if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted data. the receiver must be programmed to check the same format. (normal default condition) logic 1 = even parity is generated by forcing an even the number of logic 1?s in the transmitted. the receiver must be programmed to check the same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced (normal default condition) lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr lcr lcr parity selection bit-5 bit-4 bit-3 x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity ?1? 1 1 1 forced ?0?
st16c550 18 rev. 5.01 lcr bit-6: when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. lcr bit-7: the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled. (normal default condi- tion) logic 1 = divisor latch and enhanced feature register enabled. modem control register (mcr) this register controls the interface with the modem or a peripheral device. mcr bit-0: logic 0 = force -dtr output to a logic 1. (normal default condition) logic 1 = force -dtr output to a logic 0. mcr bit-1: logic 0 = force -rts output to a logic 1. (normal default condition) logic 1 = force -rts output to a logic 0. mcr bit-2: logic 0 = set -op1 output to a logic 1. (normal default condition) logic 1 = set -op1 output to a logic 0. mcr bit-3: logic 0 = set -op2 output to a logic 1. (normal default condition) logic 1 = set -op2 output to a logic 0. mcr bit-4: logic 0 = disable loop-back mode. (normal default condition) logic 1 = enable local loop-back mode (diagnostics). mcr bit 5-7: not used and set to ?0?. line status register (lsr) this register provides the status of data transfers between. the st16c550 and the cpu. lsr bit-0: logic 0 = no data in receive holding register or fifo. (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo. lsr bit-1: logic 0 = no overrun error. (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when addi- tional data arrives while the fifo is full. in this case the previous data in the shift register is overwritten. note that under this condition the data byte in the receive shift register is not transfer into the fifo, therefore the data in the fifo is not corrupted by the error. lsr bit-2: logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. lsr bit-3: logic 0 = no framing error (normal default condition). logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-4: logic 0 = no break condition (normal default condi- tion) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. lsr bit-5: this bit is the transmit holding register empty indi- cator. this bit indicates that the uart is ready to accept a new character for transmission. in addition,
st16c550 19 rev. 5.01 this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr bit-6: this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr bit-7: logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when there are no remaining lsr errors in the rx fifo. modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device that the st16c550 is connected to. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. msr bit-0: logic 0 = no -cts change (normal default condition) logic 1 = the -cts input to the st16c550 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-1: logic 0 = no -dsr change (normal default condition) logic 1 = the -dsr input to the st16c550 has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-2: logic 0 = no -ri change (normal default condition) logic 1 = the -ri input to the st16c550 has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. msr bit-3: logic 0 = no -cd change (normal default condition) logic 1 = indicates that the -cd input to the has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-4: cts (active high, logical 1). normally this bit is the compliment of the -cts input. in the loop-back mode, this bit is equivalent to the rts bit in the mcr register. msr bit-5: dsr (active high, logical 1). normally this bit is the compliment of the -dsr input. in the loop-back mode, this bit is equivalent to the dtr bit in the mcr register. msr bit-6: ri (active high, logical 1). normally this bit is the compliment of the -ri input. in the loop-back mode this bit is equivalent to the op1 bit in the mcr register. msr bit-7: cd (active high, logical 1). normally this bit is the compliment of the -cd input. in the loop-back mode this bit is equivalent to the op2 bit in the mcr register. scratchpad register (spr) the st16c550 provides a temporary data register to store 8 bits of user information.
st16c550 20 rev. 5.01 st16c550 external reset conditions registers reset state ier ier bits 0-7 = logic 0 isr isr bit-0=1, isr bits 1-7 = logic 0 lcr, mcr bits 0-7 = logic 0 lsr lsr bits 0-4 = logic 0, lsr bits 5-6 = logic 1 lsr, bit 7 = logic 0 msr msr bits 0-3 = logic 0, msr bits 4-7 = logic levels of the input signals fcr bits 0-7 = logic 0 signals reset state tx logic 1 -op1 logic 1 -op2 logic 1 -rts logic 1 -dtr logic 1 -rxrdy logic 1 -txrdy logic 0 int logic 0
st16c550 21 rev. 5.01 ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 1w ,t 2w clock pulse duration 17 17 ns t 3w oscillator/clock frequency 16 24 mhz t 4w address strobe width 35 25 ns t 5s address setup time 5 0 ns t 5h address hold time 5 5 ns t 6s chip select setup time 5 0 ns t 6h chip select hold time 0 0 ns t 6s' address setup time 10 5 ns see note 1 t 7d -ior delay from chip select 10 10 ns t 7w -ior strobe width 77 38 ns t 7w' chip select width 77 38 ns t 7h chip select hold time from -ior 0 0 ns t 7h' address hold time 5 5 ns see note 1 t 8d -ior delay from address 10 10 ns t 9d read cycle delay 77 38 ns t 11d -ior to -ddis delay 15 10 ns 100 pf load t 12d delay from -ior to data 35 25 ns t 12h data disable time 25 15 ns t 13d -iow delay from chip select 10 10 ns t 13w -iow strobe width 27 15 ns t 13w' chip select width 77 38 ns t 13h chip select hold time from -iow 0 0 ns t 14d -iow delay from address 10 10 ns t 15d write cycle delay 77 38 ns t 16s data setup time 20 15 ns t 16h data hold time 5 5 ns t 17d delay from -iow to output 50 40 ns 100 pf load t 18d delay to set interrupt from modem input 40 35 ns 100 pf load t 19d delay to reset interrupt from -ior 40 35 ns 100 pf load t 20d delay from stop to set interrupt 1 1 rclk t 21d delay from -ior to reset interrupt 45 40 ns 100 pf load t 22d delay from stop to interrupt 45 40 ns t 23d delay from initial int reset to transmit 8 24 8 24 rclk start t 24d delay from -iow to reset interrupt 45 40 ns t 25d delay from stop to set -rxrdy 1 1 rclk t 26d delay from -ior to reset -rxrdy 45 40 ns t 27d delay from -iow to set -txrdy 45 40 ns t 28d delay from start to reset -txrdy 8 8 rclk t r reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 rclk note 1: applicable only when -as is tied low. symbol parameter limits limits units conditions 3.3 5.0 min max min max
st16c550 22 rev. 5.01 absolute maximum ratings supply range 7 volts voltage at any pin gnd - 0.3 v to vcc +0.3 v operating temperature -40 c to +85 c storage temperature -65 c to 150 c package dissipation 500 mw dc electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. symbol parameter limits limits units conditions 3.3 5.0 min max min max v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low level -0.3 0.8 -0.5 0.8 v v ih input high level 2.0 vcc 2.2 vcc v v ol output low level on all outputs 0.4 v i ol = 5 ma v ol output low level on all outputs 0.4 v i ol = 4 ma v oh output high level 2.4 v i oh = -5 ma v oh output high level 2.0 v i oh = -1 ma i il input leakage 10 10 a i cl clock leakage 10 10 a i cc avg power supply current 1.3 3 ma c p input capacitance 5 5 pf
st16c550 23 rev. 5.01 clock timing t3w - baudout 1 /2 -baudout 1 /3 -baudout 1 /3> -baudout t1w t2w e xternal clock x450-ck- 1
st16c550 24 rev. 5.01 general write timing when using -as signal. general read timing when using -as signal - as a 0-a2 - cs2 c s1-cs0 - iow i ow d 0-d7 t4w t5s t5h t6s t6h t13w t13d t13h t15d t16s x550-wd- 1 t14d t16h valid address valid active data - ddis d 0-d7 t12d t12h x550-rd-1 - as a 0-a2 - cs2 c s1-cs0 - io r i or t4w t5s t5h t6s t6h t7w t7d t7h t9d t11d t11d t8d valid address valid active data active
st16c550 25 rev. 5.01 general read timing when -as is tied to gnd general write timing when -as is tied to gnd a0-a2 -cs -ior d0-d7 t6s' t7w t7h' t9d t12d t12h active data valid address active valid address active t6s' t7h' t12d t12h t7w? a0-a2 -cs -iow d0-d7 t6s' t13w t7h' t15d t16s t16h active data valid address active valid address active t6s' t7h' t16s t16h t13w?
st16c550 26 rev. 5.01 modem input/output timing - iow i ow - rts - dtr - cd - cts - dsr i nt - ior i or - ri t17d t18d t18d t19d t18d x450-md- 1 active active change of state change of state active active active change of state change of state change of state active active
st16c550 27 rev. 5.01 receive timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit r x next data start bit i nt - ior i or t20d t21d 16 baud rate clock x450-rx-1 active
st16c550 28 rev. 5.01 receive ready timing in non fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit r x next data start bit - rxrdy - ior i or t25d t26d x550-rx-2 active data ready active
st16c550 29 rev. 5.01 receive ready timing in fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit r x first byte that reaches the trigger level - rxrdy - ior i or t25d t26d x550-rx-3 active data ready active
st16c550 30 rev. 5.01 transmit timing stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit t x i nt t22d t24d 16 baud rate clock iow/ -iow t23d active active active tx ready
st16c550 31 rev. 5.01 transmit ready timing in non fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit t x next data start bit - txrdy t28d x550-tx- 2 -iow iow t27d byte #1 active active transmitter ready transmitter not ready
st16c550 32 rev. 5.01 transmit ready timing in fifo mode stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit t x - iow i ow d 0-d7 - txrdy byte #16 t28d t27d x550-tx-3 fifo full active
st16c550 33 rev. 5.01 package outline drawing 44lead plastic leaded chip carrier (plcc) 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1 symbol min max min max inches millimeters a r h 2 h 1 e d 3 d 2 d 1 d c b 1 b a 2 a 1 4.57 1.14 1.22 1.42 16.00 16.66 17.65 0.32 0.81 0.53 ------ 3.05 4.19 0.64 1.07 1.07 1.27bsc 12.70 typ 14.99 16.51 17.40 0.19 0.66 0.33 0.51 2.29 0.180 0.045 0.048 0.056 0.630 0.656 0.695 0.013 0.032 0.021 ----- 0.120 0.165 0.025 0.042 0.042 0.50 bsc 0.500 typ 0.590 0.650 0.685 0.008 0.026 0.013 0.020 0.090 note: the control dimension is the inch column
st16c550 34 rev. 5.01 symbol min max min max inches millimeters a b a 2 a 1 1.20 0.27 1.05 0.15 1.00 0.17 0.95 0.05 0.047 0.011 0.041 0.006 0.039 0.007 0.037 0.002 note: the control dimension is the millimeter column d c 7.10 9.20 0.20 6.90 8.80 0.09 0.280 0.362 0.008 0.272 0.346 0.004 d 1 l e 7 0.75 0 0.45 0.50bsc 7 0.030 0 0.018 0.20 bsc 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c 48 lead thin quad flat pack (tqfp) package outline drawing
st16c550 35 rev. 5.01 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet april 2005 send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com reproduction, in part or whole, without prior written consent of exar corporation is prohibited. explanation of data sheet revisions: from to changes date 4.20 4.30 added revision history. added device status to front page. sept 2003 4.30 5.00 updated ac timing values for iow, cs and ior pulse widths and read/write cycle delays. this applies to devices with top mark date feb 2005 code of "b2 yyww" and newer. 5.00 5.01 corrected the ac timing values. added chip select width for apr 2005 clarification.

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